Timing track recording apparatus



Sept. 8, 1959 D. L.. CURTIS 2,903,677

TIMING TRACK RECORDING APPARATUS Filed Jan. 13, 1956 5 Sheets-Sheet 1 /NVEN TOR AroR/vy Sept. 8, 1959 D. L. CURTIS 2,903,677

TIMING TRACK RECORDING APPARATUS Filed Jan. 13, 1956 5 Sheets-Sheet 2Cpl CPS

VOLTAGE ATTORNEY Sept. 8, 1959 Filed Jan. l5, 1956 D. l.. CURTIS2,903,677

TIMING TRACK RECORDING APPARATUS 5 Sheets-Sheet 3 Fig. 3b

DAN/EL L um/s,

/NVENroR @www ATTORNEY Sept. 8, 1959 D. L. CURTIS 2,903,677

TIMING TRACK RECORDING APPARATUS Filed Jan. 1s, 195e 5 vsheets-smeet 4 lI i +2501/ i l I 60, 6 6 6/5 I i 606 602 /607 0u/ l l 6/4 i 26?/ /2 g OBg /e/a I A 7 l- I v .L E 55 l. l i 605 I 604 l/ I 'L :Ll

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/A/ VE N TO/P ATT/PNEY Sept. 8, 1959 D. L. cURTls TIMING TRACK RECORDINGAPPARATUS 5 Sheets-Sheet 5 Filed Jan. 15, 1956 m lll. U l C M y T E L MM uw .n M A n D v, B lo llllllllllllllllllllllllllllllllllllll l.. -l l1 l I l l x l NBG NOG N N IN @+Qu @I Q @V N l l G n ab c n MG u NG S NON\DN u NQ G G lo@ Q6@ ln@ n Q0@ I ma@ llnwm |lnh@ ;1. lo@

United States Patent O i TllVllNG TRACK RECORDING APPARATUS Daniel L.Curtis, Manhattan Beach, Calif., assigner to Hughes Aircraft Company,Culver City, Calif., a corporation of Delaware Application January 13,'1956, Serial No. '558,990

9 Claims. (Cl. 340-174) This invention relates to recording systems andmore particularly to a system for recording a continuous timing track ofuniformly spaced clock pulses on a recording channel of a computermemory drum.

In certain digital computing machinery all operations are timed orsynchronized by clock or timing signals which are essentially uniformlyspaced electrical pulses. In order to insure reliable operation of adigital computer, it is essential that the clock pulses be of constantamplitude, be accurately and uniformly spaced and thus free from timemodulation, and in addition do not contain transient and spurioussignals.

In a digital computer employing a rotating drum-type memory, it isconventional and highly convenient to reserve a memory channel on thedrum for recording a timing track of uniformly spaced clock pulses. Toaccomplish this, either a rectangular or sine wave signal of constantfrequency is initially recorded on the channel which, when reproduced,will provide uniformly spaced clock pulses for synchronizing the otheroperations of the computer. v

Although this method of providing clock pulses is highly eilicient intheory since the digital computer thereby supplies its own synchronizingsignals which are synchronized with the rotation of the drum, muchdifficulty has been encountered in the past in accurately and reliablyrecording the timing track on the drum. Among the most serious problemsencountered are the difliculty of recording precisely uniformly spacedsine or rectangular Wave signals to produce a timing track of the exactdesired number of cycles with accurate inphase overlap between theorigin and terminal end of the timing track Without the introduction oftransient or other spurious undesired signals.

Although it is possible to utilize a crystal-controlled oscillator as asource of constant frequency signals for re cording on the timing trackof the drum, it is extremely difficult to maintain the angular velocityof the rotating drum suflciently constant to accurately record thedesired signal. Even a monentary slight variation in angular velocity ofthe drum will cause out-of-phase overlapping of the recorded timingtrack, thus resulting in a discontinuous track. For the same reason itis difficult to record a timing track having precisely the desirednumber of recorded pulses around the circumference of the timing trackchannel.

It is apparent, therefore, that in order to accurately and reliablyrecord a timing track on the rotating memory drum of a digital computer,the frequency of the signals being recorded on the channel must beregulated at all times in accordance with the instantaneous angularvelocity of the drum itself. In other Words, there must be aninterdependent relationship between the angular velocity of the rotatingdrum and the frequency of the signals being recorded on the timingtrack. Such a relationship has been attempted in the past by variousmechanical and electromechanical systems for linking the angular motiona A 2,903,677 ICC Patented Sept- 8 '1959 of the drum with the signalsource utilized for recording the timing track. Most prominent amongthese systems have been the etching or grooving system, the toothed-Wheel system, and the crystal controlled oscillator synchronous-motorsystem.

The etching or grooving system, as the name implies', at tempts tosynchronize the frequency or repetition rate of the signals recorded onthe timing track with the rotational velocity of the drum by directlyetching or grooving a timing track on the drum. This is accomplished byeither etching or cutting a series of slots around the periphery of thedrum thereby producing a variable magnetic reluctance path to serve as atiming track. When the drum is rotated, a magnetic reading head isstationed above the lsurface of the timing track for producingVelectrical clock pulse signals corresponding to the variable reluctancepath of the etched or machined timing track. In addition to thelaborious nature of the etching or machining process, this method hasmany other inherent disadvantages, among which are the mechanical errorsintroduced in machining or etching the grooves and the inability toreadily vary the number of clock pulses recorded on the timing track.

In the toothed-wheel system, signals for recordation on the timing trackare derived from a toothed Wheel which is mechanically coupled to therevolving drum and rotated thereby. Electrical signals for recording thetiming track on the drum are derived from a magnetic reading headstationed near the peripheral surface of the toothed Wheel, anelectrical signal being produced by the head upon passage of each toothof the wheel in proximity of the reading head. Although this system hasthe advantage of permitting a selection of the number of pulses recordedon the timing track of the drum by exchanging Wheels containing adilerent number of teeth, this system is subject to errors introduced bythe mechanical play inherent in all known mechanical coupling devices.For example, the play inherent in the mesh of even a high precision geartrain is suicient to introduce considerable time modulation in a seriesof pulses produced by this system. In addition, the play in the couplingmeans employed causes an in-phase overlapping of the timing trackproduced to be a result of chance rather than be a certainty. It will beapparent that if the toothed Wheel is directly coupled to the revolvingdrum in order to eliminate coupling errors the system becomes tantamountto the grooving system previously discussed.

In the crystal controlled oscillator synchronous-motor system, a commonsignal source is utilized for controlling both the speed of rotation ofthe memory drum and the frequency or repetition rate of the signalsrecorded on the timing track of the drum. In practice, constantfrequency signals are produced by a crystal controlled oscillatorserving yas a signal source. These signals are amplified and utilizedfor energizing a synchronous motor and also for recording clock pulseson the timing track of the drum. The drum is directly coupled to thesynchronous motor and rotated thereby. In this manner the rotational velocity of the drum and the frequency of the signals recorded on thetiming track are both controlled from a common primary source.

In actual practice, the crystal controlled oscillator syn#chronous-motor system has certain inherent disadvantages'. Any variationin the frequency of the signals from the primary signal source will beinstantaneously effective to alter correspondingly the frequency of thesignals recorded on the timing track of the drum. Due to the relativelylarge inertia of the drum, however, a time lag occurs between changes infrequency of the primary source and any corresponding change in angularvelocity of the drum. This not only results in temporarily erraticaguas?? recording of the timing track but starts a hunting effectwherein the motor and drum attempt to maintain an angular velocitycorresponding to the frequency of the primary signals. Although it istheoretically possible to minimize this hunting eifect by utilizing asufciently large synchronous motor, the resulting system becomes largeand ineflicient since the advantages of utilizing the synchronous motorno longer apply after the timing track is recorded and the drum isrevolved for other operations of the digital computer.

Accordingly, it is an object of the present invention to provide asystem for rapidly recording a continuous timing track around arecording channel of a rotating memory drum.

Another object of the present invention is to provide a system of thetype referred to which will record a timing track of uniformly spacedclock pulses around a recording channel of a memory drum.

It is also an object of the present invention to provide a recordingsystem of the type referred to which will record a timing track of anydesired number of clock pulses on the drum independent of the rotationalvelocity thereof.

A still further object of the present invention is to provide a systemof the class referred to which is not subject to mechanical errors forrecording a continuous timing track with irl-phase overlap and free fromtransient and other spurious signals.

According to the basic concepts of the present invention, a timing trackof any desired number of clock pulses is obtained on a continuouslyrotating magnetic memory drum by continually recording clock pulses ortiming signals on the timing track of the drum in a manner whereby eachpulse as it is recorded erases any previously recorded pulse recorded onthe same spot of the drum. rl`he frequency or repetition rate of theclock pulses being recorded on the drum is then varied until a timingtrack of exactly the desired number of clock pulses with in-phaseoverlap has been recorded on the drum. When this has been achieved, therecording of the timing track is interrupted in a manner to preserve thedesired recorded track free from transient or other unwanted spurioussignals.

The above process is accomplished by comparing, at the end of eachrevolution of the drum, the number of clock pulses recorded during thatrevolution with the number of clock pulses desired. As a result of theabove comparison process, the frequency of the signals being recorded onthe timing tracks are altered appropriately until exactly the desirednumber of clock pulses has been recorded during a previous revolution ofthe drtun. When this has occurred, minute frequency adjustment is madeuntil there is an in-phase overlap of the timing track, at which timethe recording is interrupted at the proper moment to provide acontinuous timing track of the desired number of clock pulses within-phase overlap. The recorded timing track is then played back to checkits accuracy.

In its basic structural form, the timing track recording system of thepresent invention comprises a variable frequency recording circuit, adrum revolution indicator, a counting circuit, and a comparator. Clockpulse signals produced by the variable frequency recording circuit arecontinuously recorded on the timing track channel of a rotating magneticdrum. The drum revolution indicator is coupled to the rotating magneticdrum in a manner to produce a revolution indicating or origin pulsesignal once during each revolution of the drum indicating the beginningof each revolution. The counting circuit is responsive to the clockpulse signals produced by the recording circuit and the origin pulse forcounting the clock pulse signals and for producing an output signal,during each revolution of the drum indicating when, during therevolution, the desired number of clock pulses has been recorded on thetiming track. The signals produced by the counting circuit and thesignals produced by the drum revolution indicator are compared for timecoincidence by the comparator circuit to determine when the exact numberof clock pulse signals desired has been accurately recorded on thetiming track.

The novel features which are believed to be characteristic of theinvention, both as to its organization and method of operation, togetherwith further objects and advantages thereof, will be better understoodfrom the following description considered in connection with theaccompanying drawings in which one embodiment of the invention isillustrated by way of example. It is to be expressly understood,however, that the drawings are for the purpose of illustration anddescription only, and are not intended as a delinition of the limits ofthe invention.

Fig. l is a schematic diagram in block form of an embodiment of thetiming track recording system of the present invention;

Fig. 2 is a chart of the voltage waveforms associated with specificportions of the timing track recording system illustrated in Fig. l;

Figs. 3a and 3b illustrate the configuration of the image appearing onthe face of the oscilloscope included in the system of Fig. l when thenumber of clock pulses recorded on the timing track of the drum isgreater than and less than the desired number of clock pulse signals;

Fig. 4 is a schematic circuit diagram illustrating the detail structureof the complementary pulse forming circuit shown in block form in Fig.1;

Fig. 5 is a detailed schematic circuit diagram of the gate circuitillustrated in block form in Fig. l;

Fig. 6 is a schematic circuit diagram of the clock writing circuitillustrated in block form in Fig. l; and

Fig. 7 is a. schematic circuit diagram, partially in block form,illustrating tin greater detail the counter and the count selectioncircuit of Fig. 1.

Reference is now made to Fig. l wherein there is presented in schematicblock form a timing track recording system in accordance with thepresent invention adapted for accurately recording a timing track Mi ofany desired number of clock pulse signals around the periphery of amagnetic memory drum ll continuously rotating in the direction,indicated by an arrow, by a driving source not shown. The signalsrecorded on timing track l@ of drum l originate in the form of sine wavesignals SWS produced by a variable frequency oscillator (VFO) 20 whichare impressed on an amplifier and squaring circuit 21 through switch S1which is normally in the A position as illustrated. The output signalsSW of ampliiier and squaring circuit 2i are substantially square wavesignals having a frequency or repetition rate coincident with the sinewave signals impressed thereon. Square wave signals SW aresimultaneously impressed on the input circuits of a complementary pulseforming circuit 22 and a pulse forming circuit 23. In response tosignals SW, complementary pulse forming circuit Z2 simultaneouslyproduces a positive and a negative triggering pulse Cpl and CD2 onoutput terminals Pfr and P2, respectively, for each cycle of square wavesignals SW, each complementary pair of pulses Cpl, Cpz being produced intime coincidence with the leading edge of the positive halfcycle of acorresponding square wave signal Sw. Simultaneousl, pulse formingcircuit 23 produces a series of negative triggering pulse CPScorresponding to the trailing edge of each positive half-cycle of squarewave signals SW impressed thereon.

Negative triggering pulses CD2, Cpg occurring successively during eachcycle of signals SW ar., impressed on the 1 and the O input circuits,respectively, of a bistable flip-dop QW'. In response to negative pulsesCpz and Cpa impressed thereon, ip-flop QW produces complementary binaryor two-level voltage signals QW, QW which may both be impressed on clockWriting circuit 12 as is conventional. Clock Writing circuit l2, inresponse to complementary signals QW and QW, develops current signals Cpwhich are magnetically recorded on timing track of drum 1 by magneticWriting head 11.

A switch S5, illustrated in the A position, provides au external groundconnection for writing circuit 12. When switch S5 is in the B position,however, the external ground connection is broken. As will becomeapparent later on from the ensuing discussion, when it is desired tointerrupt the recording of clock-pulse current signals Cp, switch S5 isthrown to the B position. As a result, clock writing circuit 12 becomesgradually inoperative, in a manner to be shown, thereby avoidingintroduction of transient signals on timing track 10 which could resultfrom a sudden cessation of the clock-pulse current signals Cp.

Flip-flop QW', similar to the remaining flip-flop circuits hereinafterdiscussed, is a conventional bistable Iiiip-ilop having l and 0 inputcircuits and producing complementary binary or two-level output signalsQW and QW representing the stable state of the flip-'flop Morespecifically, a ilip-flop of this class is characterized by producing arelatively high-level QW and a relatively 10W-level QW output signalwhen in one of its stable states, and a relatively low-level andhigh-level QW and QW output signal, respectively, when in its otherstable state. For convenience, a relatively high-level output signal ofa flipflop will hereinafter be referred to as a l-level signal, and arelatively low-level output signal as a O-level signal. Although thetiming track recording system of the present invention is in no way solimited, it is herein assumed that a relatively high or l-level voltagesignal is a ground or zero potential signal, and that a relatively lowor O-level signal is a volt signal. It is also convenient to considerone of the complementary output signals of a nip-flop as the true outputsignal of the flip-flop and the other output signal of the Hip-flop asthe true-complement output signal. In accordance with this convention,the true output signal is indicated by a symbol without a oar over thesignal, and the true-complement output signal by the same symbol withthe In order to avoid possible confusion, it should be vunderstood atthe outset that a binary signal or variable as herein used indicated bya symbol with a bar over the symbol indicates the complement of thesignal or variable. More specifically, a binary signal represented by asymbol with a bar over the signal is at all times at the oppositevoltage level as a signal represented by the same symbol without the barThus output signal QW represents the true output signal and outputsignal QW the true-complement output signal of flip-flop QW'.

In order to provide terminology for identifying the stable states of aconventional bistable flip-flop of this class, the stable state of aflip-flop characterized by a 1level true output signal will hereinafterbe referred to arbitrarily as the l-representing state, and the oppositestate characterized by a O-level true output signal will be referred toas the O-representing state.

A conventional bistable ip-op, such as QW of Fig. 1, is furthercharacterized by assuming the l-representing state in response to apulse applied to the 1 input of the flip-flop, and conversely byassuming the O-representing state when a pulse is applied to the 0 inputof the flip-flop. Thus flip-flop QW' will assume the l-representingstate in response to each Cp2 negative pulse and will assume the0-representing state in response to each CP2 negative pulse impressedthereon. Although not pertinent at this point since signals CP2 and Cp3correspond to the leading and trailing edges, respectively, of squarewave signals SW and therefore never occur simultaneously, it should beunderstood that a flip-flop of this class is triggered to its oppositestate, regardless of its previous state, when a pulse is simultaneouslyapplied to both the l and 0 inputs of the flip-flop. Typical ip-ops of 6l Y the above class are illustrated and described in detail in U.S.Patent No. 2,644,887, entitled Synchronizing Generator, by A. E. Wolfe,Jr., issued July 7, 1953.

Having thus far described the variable frequency recording circuit ofthe timing track recording system illustrated in Fig. l comprised of VFO2G, amplifier and squaring circuit 2l, complementary pulse formingcircuit 22, pulse forming circuit 23, ilip-op QW', clock writing circuit12, and magnetic writing head 11, it is advantageous at this time toconsider more closely the waveforms of the signals heretofore discussedbefore proceeding to the remaining portions of the system. Accordingly,reference is made to Fig. 2 wherein a waveform chart is presentedillustrating the voltage wave shapes at various points in the timingtrack recording system of Fig. 1 plotted as a function of time.

Each signal illustrated is identied by a symbol at the extreme left endof Fig. 2 which directly corresponds to the reference symbol utilized toidentify the corresponding signal in Fig. l. For example, sine wavesignals SWs appearing at the output of VFO 20 of Fig. l are illustratedon line SWs of the wave chart. In like manner, the remaining signalsillustrated in the wave chart are readily identifiable by reference toFig. 1.

It is noted by an examination of the chart of Fig. 2 that each cycle ofsquare wave signals SW coincides in time with a corresponding cycle ofsine wave signals SW. It is further noted that both a positive Cpl pulseand a negative CD2 pulse are produced by complementary pulseformingcircuit 22 during each cycle of square wave signals SW corresponding tothe leading edge of each cycle. In contrast, a negative Cps pulse isproduced by pulseforming circuit 23 during each cycle of square wavesignals SW coincident with the trailing edge of each cycle.

Since signals CD2 and CD3 are applied to the 1 and O inputs of flip-nopQW', it is triggered to the 1represent ing state by each CP2 signal andtriggered to the O-representing state by each Cp3 signal. As a result,the true output voltage level signals QW of the flip-flop, asillustrated in the voltage chart of Fig. 2, corresponding to signal SWare l-level signals for each interval of time between a CP2 signal andthe immediately following Cpa signal. Conversely, signals QW are O-levelsignals for each interval of time between a C53 signal and theimmediately succeeding CD2 signal. The true-complement signals QW offlipiiop QW are shown in the wave chart as having at all timescomplementary values to signals QW. Clock pulse current signals CD havesubstantially the waveform indicated in the chart, this waveform havingthe proper characteristics for exciting writing head 11 to magneticallyrecord on channel 1d of drum 1 clock pulses substantially identical tosquare wave signals SW.

The circuit of Fig. 1 described thus far relates to that portion of thetiming track recording system of the present invention for recordingsubstantially rectangular clock pulses on timing track 16 of drum 1.Assuming that magnetic drum 1 is rotated at a substantially constantangular velocity, it is evident from the previous discussion, that thenumber of clock pulses recorded on drum 1 during any particularrevolution of the drum will be directly dependent upon the relativefrequency of the sine wave signals SWs produced by VFO 20 compared tothe angular speed of the drum. It remains, therefore, to consider theelements of the timing track recording system of Fig. l which areutilized for determining when the frequency of signals SWS has beenproperly adjusted to produce the desired number of clock pulses withinphase overlap on channel l0 of drum 1. At this time switch S5 may bethrown to the B position for gradually interrupting the clock-pulserecording.

With reference to Fig. 1, it will be noted that in addition to switchesS1 and S5 previously discussed, there are three further switches S2, S3and S4 in the circuit as will be more fully explained hereinafter. Forconvenience in the ensuing description, it will be assumed that al1nenas?? switches Sl to S5 inclusive are each in the A position shown inFig. 1 unless specifically stated otherwise. As has been previouslymentioned, the timing track recording system of the present invention isnot only adapted for recording a timing track It) on drum 1 of anydesired number of clock pulses, but in addition is also adapted todetermine the number of clock pulses and the nature of the phase overlapof a previously recorded timing track. T accomplish this latter functionswitches Sl to S are thrown to their respective B positions.

In order to time the operation of the remaining portions of the circuitof Fig. 1 With the rotation of drum 1, a drum revolution indicator isprovided by magnetically recording a single pulse 3i on an origin pulsechannel 26 of the drum. Pulse 3l is read by a magnetic reading head 27which produces an origin pulse signal Ops once each revolution ofdrum 1. Origin pulse signals Ops are impressed on a reading amplifierand squaring circuit 2S, similar to amplifier and squaring circuit 21,for amplifying and shaping signals Ops to produce a substantiallyrectangular origin pulse Op during each revolution of the drum.

Origin pulses Op and complementary pulses Cpl, Cp2, producedrespectively by the drum revolution indicator and the variable frequencyrecording circuits previously described, are applied to a countingcircuit comprised of a gate circuit 23a, a ip-lop Qpp, a counter 24, anda count selection circuit 25. Positive pulses Cpl and origin pulses Opare impressed on gate circuit 23a which also receives thetrue-complement output signals Qpp of ip-op Qpp. Gate circuit 23aselectively gates signals Cpl to produce output signals (Cpl.)p.pp)hereinafter referred to as signals Tp when, and only When, both signalsOp and @Op are simultaneously l-level signals. It is apparent,therefore, that each Tp signal is in reality a Cpl signal which has beenimpressed on gate circuit 23a coincident with an origin pulse Op duringits high or l-level value, and with a 1-level @Op signal. As aconsequence, output signals Tp are identied by the signals impressed ongate circuit 23a, Where a dot between each of the signals indicates alogical and function as utilized in conventional Boolean logic.

Signals Tp produced by gate circuit 23a, and signals Cp2 produced bycomplementary pulse forming circuit 22 are impressed on the 1 and the 0input circuits, respectively, of hip-flop Qpp. Negative pulses Cp2 andoutput signals Qpp, Qpp, of flip-flop Qpp are impressed on counter Z4.

Counter 24 may be any conventional electronic counter with certainadditional features, capable of counting negative pulses Cp2 impressedthereon and producing cornlementary pairs of binary or two level outputsignals Ql, Q1; Q2, Q2; Q3, Q3; Qny @n indicating the Count contained incounter 24, in a true binary or a binarycoded numbering system. Theadditional features required of counter 24 are (l) that signals Cp2 becounted by the counter only during the time that signals Qpp and Qpp arerespectively O-level and l-level signals, and (2) that counter 24- bereset to zero whenever signals Qpp and @op are respectively l-level andO-level signals. rhus counter 24 counts signals Cp2 when flip-flop Qppis in the O-representing state and is reset to Zero Whenever the ip-iopassumes the l-representing state.

Count selection circuit 25 is coupled to counter 24 and responsive tocount signals Ql, Ql; to Qn, Qn, produced by counter 24, for producingtirst and second count selection pulses Cl and C2 on its outputterminals Cl and C2', respectively. More specifically, count selectioncircuit Z5 may be preset to provide a r'irst positive pulse Cl on outputterminal Cl at any desired count of counter 24, and in addition may alsobe preset to produce a second positive pulse C2 on output terminal C2 atany second count of the counter.

In operation, the counting circuit of the timing track recording systemof the present invention functions in the following manner. During eachrevolution of drum I, flip-flop Qpp is normally maintained in theO-representing state since signals Cpl are blocked by gate circuit 23a,from appearing at the 1input of the dip-flop and signals Cp2 aredirectly applied to the O-input of the hip-flop. Accordingly, counter 24counts pulses Cp2.

Once during each revolution of drum l, when an origin pulse Op isapplied to gate circuit 23a, a single Tp signal is impressed on thel-input of flip-flop Qpp coincident with a corresponding Cp2 signalimpressed on the O-input of the flip-flop. As a result, dip-flop Qop istriggered to the opposite or l-representing state. When this occurs,counter 24 is reset to zero. The immediately succeeding Cp2 pulsetriggers flip-fiop Qpp' back to the O-representing state in which stateit again remains until the occurrence of the next origin pulse Op. Inthis manner, counter 24- is made to begin counting the number of clockpulses being recorded on drum il during each revolution of the drum atexactly the same point in space around the periphery of the drum.

In operation, count selection circuit 25' is adjusted, by means to beexplained later on, to produce a positive Cl signal on terminal ClWhenever output signals Ql, Q2 to Qm Qn from counter 24 indicate thatthe number of clock pulses which it is desired to record on timing trackl@ of drum 1 have been counted by the counter. Count selection circuit2S is also adjusted to produce a positive C2 signal on terminal C2slightly in advance of each Cl signal as an alert or Warning signal (seeFig. 2).

For example, assume that it is desired to record 1,000 clock pulses ontiming track i@ of drum I. Count selection circuit 25 would then beadjusted to produce a Cl signal on terminal Cl' Whenever signals Ql, @lto QTL, Qn indicate that counter 24 has counted 1,000 Cp2 signals. inorder to provide an alert or Warning signal, selection circuit 25 wouldalso be adjusted to produce a C2 signal preceding in time each Cl signalby a convenient period as for example at each count of 994 of counterZit.

From the preceeding discussion, it is apparent that flipliop Qpp istriggered to the l-representing state once each revolution of drum by apositive Cpl pulse occurring in time coincidence with an origin pulseOp. It is further apparent that flip-flop Qpp Will be triggered back tothe D-representing state by the immediately succeeding Cp2 pulse. Thetrue output signal Qpp of flipflop Qpp', therefore, is a 0-level signalat all times during each revolution of drum 3l except for a period oftime corresponding to a single cycle of square Wave signal Sw occurringin time-coincidence with an origin pulse Op, This is illustrated in Fig.2 wherein it is noted that signal Qpp has a l-level value for a periodcommencing with pulse (Cplptjop) and ending with the succeeding Cplpulse. Conversely, the true-complement output signal Qpp of flip-flopQpp has a l-level value at all times during each revolution of drum l,except for the above described period when it has a O-level value.

As previously explained, signal Cl, produced by count selection circuit25, has a 0-level value at all times during each revolution of drum 1except for a period of time corresponding to one cycle of square Wavesignal SW indicating when, during the revolution of the drum, thedesired number of clock pulses has been recorded on the timing trackitl. Earlier in time during each revolution of drum i, a l-level Clsignal is produced. Depending upon the setting of the count selectioncircuit 25, a predetermined number of cycles of signals SW separate thel-level periods of signals Cl and C2 during each revolution of drum l.For example, in Fig. 2 the l-level period of signal C2 is illustrated asoccurring six cycles of signal S in advance of the l-level period ofsignal Cl. 1for convenience in future discussion, the brief periodduring each revolution of drum l when a Qpp, a Cl, and a C2 signal is al-level signal, it will hereinafter be referred to respectively as apositive Qpp, Cl, and C2 pulse. In a similar 9 manner, the brief periodduring each revolution of drum when Qop signal is a -level signal willhereinafter be referred to as a negative Q01, pulse.

From the foregoing discussion, it is evident that either negative pulsesQ01, 0r positive pulses QOp may be utilized as a reference indicatingthe instant each revolution of drum 1 begins. For this reason, signalsQ09, @Op may be considered as revolution indicating signals, and gatecircuit 23 and flip-flop Qop as part of a drum revolution indicatingcircuit.

During each revolution of drumr ll, on the other hand, a positive pulseC1 indicates the exact moment during the revolution of the drum when thedesired number of clock pulses has already been recorded on timing track10. By comparing for coincidence during each revolution of the drum,therefore, either signal Qp or @Op with signal C1, it may be ascertainedwhen the desired number of clock pulses has been recorded around theperiphery of timing track of drum 1 with in-phase overlap during thepreceding revolution of the drum.

In the embodiment illustrated in Fig. 1, an oscilloscope 30 is utilizedfor determining when the above discussed coincidence has occurred. Infurtherance of this objective, positive pulses C1, produced by countselection circuit 25, are applied to the Y-axis of oscilloscope 30 byway of terminal Y. The internal X-axis sweep-circuit of oscilloscope 30is then adjusted to produce a convement-sized image 33 of positivepulses C1 on the face of cathode ray tube CRT of the oscilloscope,Positive pulses C2 are then applied through switch S3 to the triggeringterminal T of the internal X-axis sweeping circuit of the oscilloscopein order to insure that image 33 of signal C1 will occupy the sameposition 0n the face of tube CRT during each revolution of drum 1.Negative pulses @Op are applied to the cathode circuit of the tube CRTof oscilloscope 30 by way of terminal Z, the cathode connection to thetube CRT being commonly referred to as a connection for the Z-axis ofthe scope. To those skilled in the art, it will be evident that eachnegative pulse Q01, impressed on the Z axis of tube CRT will cause amomentary decrease in the cathode potential thereby causing acorresponding momentary increase in intensity producing an intensifiedspot 32 on trace or image 33.

If the number of clock pulses recorded on timing track 10 of drum 1exceeds the desired number of pulses, to which count selection circuit25 has been pre-set, a positive pulse C1 will occur in advance of anegative @op pulse during each revolution of the drum. When this occurs,the intensified spot 32 will not be centered as illustrated in Fig. l,but will occur after the image 33 of pulse C1 as illustrated in Fig. 3a.Conversely, if the number of count pulses recorded on timing track 10 ofdrum 1 is less than the desired number of clock pulses, a negative @oppulse will occur before a positive pulse C1 is produced during eachrevolution of the drum. As a result, counter 24 is reset to zero duringeach revolution of the drum before the counter has a sufficient count toproduce a C1 signal. Consequently, the intensity spot 32 will occur onthe left edge of the trace as illustrated in Fig. 3b, wherein noreproduced image of a C1 pulse is produced. If the exact number ofdesired clock pulses is recorded on timing track 10 of drum 1 duringeach revolution of the drum, however, negative pulses Q01, and positivepulses C1 occur in exact time coincidence, i.e., exactly the same timeduring each revolution of the drum. When this occurs, intensity spot 32will occur at the exact center of the reproduced image 33 of positivepulses C1 during each revolution of the drum, as indicated in Fig. 1.

The position of intensity spot 32 with respect to the reproduced image33 of positive pulses C1 may be varied by altering the frequency of sinewave signals Sws thereby altering the repetition rate of clock pulsesCp. For example, if intensity spot 32 occurs to the right of image 1032, as is illustrated in Fig. 3a, the spot may be moved to the left bydecreasing the frequency of signals SW. With equal ease, when spot 32appears on the left edge of the trace CRT 31, as illustrated in Fig. 3b,the spot may be gradually shifted toward the right by correspondinglyincreasing the frequency of signal Sw. In this manner the position ofintensity spot 32 with relation to pulse trace 33 may be adjusted byadjusting correspondingly the frequency of signals Ss until the exactdesired coincidence illustrated in Fig. l has been achieved. If therecording of clock pulses Cp is interrupted at this time, by throwingswitch S5 from the A to the B position, the desired timing track 10 ispreserved on drum 1.

Having explained the operation of the system of the present inventionillustrated in Fig. l for recording a timing track 1G of a desirednumber of clock pulses with in-phase overlap, the procedure employed forutilizing the recording system of Fig. l to check a timing trackpreviously recorded will now be explained. To perform this function, thecontacts of all switches S1 to S5 are thrown -to the respective Bcontact positions. When this is done it will be noted that variablefrequency oscillator 20 is disconnected from the remaining portion ofthe circuit. The signals formerly applied to the input of amplifier andsquaring circuit 21 from oscillator circuit 20 are now supplied from amagnetic reading head 35 positioned above timing track 10 and producingelectrical signals corresponding to the previously recorded clockpulses. Thus, the signals previously recorded on timing track T0 are nowampliiied and squared by amplifier and squaring circuit 21 to formsignals SW. Signals SW, as before, are simultaneously applied tocomplementary pulse forming circuit 22 and pulse forming circuit 23, theoutputs o-f which are respectively applied to the l and G inputs offlip-flop QW producing output signals QW and QW which are applied toclock writing circuit 12. However, since switch S5 is now in the Bposition, clock writing circuit 12 is inoperative for reasons more fullyexplained later on.

Since switch S2 is now in the B position, output signals remainingcircuit and are, therefore, ineffective during the checking operation.It is, accordingly, evident that the only signals produced by therecording portion of the system of Fig. l which are effective in theremaining circuit are signals CP2 which are simultaneously applied tocounter 24 and the 0 input of hip-flop Qop. It will be observed thatsince switch S2 is in the B position, signals C1 produced by countselection circuit 25 are now applied to the l input of hip-Hop Qop aswell as to terminal Y of oscilloscope Sil. Signals C2, produced by countselection circuit 25, are isolated from the remaining circuits andorigin pulse signals Op are now applied through the B contact of switchS3 to the trigger -terminal T of oscilloscope 36. Oscilloscope 3) istherefore triggered once during each revolution of the drum by originpulses Op.

Counter 24 now recycles on the count representing the desired number ofclock pulses. This is readily understood when it is remembered thatcounter 2d is reset whenever flip-dop Qop is in its l-representingstate; flipop Qop being now set to its l-representing state by signal C1applied through switch S2. The intensication terminal Z of oscilloscope3th now receives negative signals Cpg through contact B o-f switch S4connected to the P2 output of complementary pulse forming circuit 22 asindicated. Summarizing, therefore, trace 33 of oscilloscope 30 is areproduction of signals C1 as before. Counter 24 is reset upon eachcompletion of a count representing the desired number of count pulsesignals, as preset in count selection circuit 25. The intensificationspot 32 is now generated by negative going pulses CP2 which aregenerated for each clock pulse signal recorded on timing track 10.

lt is apparent, therefore, that since origin pulses Op are impressed onthe horizontal trigger terminal T of oscilloscope 30 and signals C1,produced by count selection circuit 25, are impressed on terminal Y ofthe oscilloscope, image 33 of pulse C1 will be stationary if the desirednumber of clock pulses has been recorded on tirning track l@ of drum l.If the number of clock pulses recorded on the timing track is in excessof the desired number of clock pulses as pre-set by count selectioncircuit 25, then the repetition rate of signal pulses C1 will be inexcess of the repetition rate of origin pulses Op. As a consequence,image 33 of pulse C1 will occur earlier in time during each revolutionof drum l as compared to pulses Op, thus causing image 33 to appear toshift across the face of CRT 31 from right to left. In other words, theoscilloscope will appear to be out of synchronism. On the other hand, ifthe number of clock pulses recorded ou timing track l@ is less than thedesired number of clock pulses, signals Op will have a repetition rategreater than the repetition rate of signal C1. Hence, image 33 willagain shift but from left to right.

lt is often desired to determine exactly the number of clock pulsespreviously recorded on timing track lil when the number recorded isdifferent from the desired number of clock pulses as determined by theabove described test. This knowledge is often useful in determining asource of error in the recording process, as for example, in determiningthe quantity of error introduced in the recording process by a gradualshifting of frequency of the variable frequency oscillator Ztl, or avarying angular velocity of rotation of drum l. Thus, in checking thecorrectness of a previously recorded timing track on drum l, if it isfound that image 33 of oscilloscope 3@ is non-stationary by the aboveoutlined procedure, the exact number of clock pulses recorded on timingtrack l@ is determined by the following process.

With switches S1 to S5 in their B positions, count selection circuit 25is pre-set to produce a C1 pulse on each second count of counter Z4. Itis then observed if a stationary image is produced on the face of tubeCRT. From the previous discussion, it is apparent that if a stationaryimage is produced, this indicates that the number 2 is a primary factorof the number of clock pulses previously recorded on timing track 10. lfthe image appearing on the face of the tube CRT is still transient,count selection circuit 2S is set to produce a C1 pulse on each thirdcount, and so on, repeating the process until a rst prime factor of thenumber of clock pulses recorded on the timing track is found. When afirst prime factor has been found by the above procedure, ie., when astationary image is obtained on the face of the tube CRT, a second primefactor is then determined by successively increasing the setting ofcount selection circuit Z5 by one unit until a second setting of countselection circuit 25' is found for producing a stationary image on theface of the tube CRT. The above process is repeated until all singledecimal digit prime factors are determined. Count selection circuit 25is then pre-set to various products of the prime factors representingvalues relatively near the number of desired clock pulses until astationary image on the face of the tube CRT is obtained. Countselection circuit 25 is then successively set at a slightly lower and aslightly higher count to determine if the pulse images produced appearto shift respectively ltowards the right and towards the left edge ofthe face of tube CRT. lf this occurs, the number of clock pulsesrecorded on the drum is then known as equal to the last stationary imagesetting of count selection circuit 2S.

An example may be utilized to further clarify the checking procedure fordetermining the number of clock pulses which has been recorded on timingtrack lil. Assume that it is desired to record exactly 1000 clock pulseson the timing track. Further assume that actually 980 clock pulses havebeen recorded. With switches S1 to S5 thrown to their B positions, andcount selection circuit 25 set to produce a C1 pulse at each lOOOthcount of counter Z4, the preliminary check for the accuracy of thetiming track il() is followed.Y Since the actual nurn-v ber of pulsesrecorded on timing track itl is 980, whereas count selection circuit 25produces a C1 pulse every lOOGth clock pulse, image 33 will not bestationary. In contrast, the oscilloscope 3u will apear to be out ofsynchronism, that is, the image will appear to drift from right to left.At this point, therefore, it is known that the actual number of clockpulses recorded on timing track lil of drum l is less than the requirednumber of clock pulses for which count selection circuit 25 is set.

The prime factors of the number of clock p-ulses actually recorded arethen checked. To this end, count selection circuit 25 is set to producea C1 pulse for every second count of counter 24. Since there areactually 98D clock pulses recorded on the timing track, a stationaryimage will be observed. In order to check the operation of the countselection circuit Z5 and counter 24 at this point, the internal sweepcircuit is expanded suiciently to clearly oberve two succeeding pulseimages on the face of the tube CRT. The number of intensi- Iicationspots, produced by application of signals CP2 on the Z terminal ofoscilloscope 3S, are then counted between two succeeding pulse images.Ir" the number of intensity spots is 2, thereby agreeing with thesetting of the count selection circuit 25, it is known that thecombination of counter 24 and count selection circuit 25 are operatingsatisfactorily.

Proceeding in the above-described manner, other prime factors of thenumber of clock pulses actually recorded on the timing track are thenobtained by selectively setting count selection circuit successively tohigher values. ln this manner it is determined that the prime factors of2, 4, 5 and 7 produce stationary images on the face of CRT 3l.

Count selection circuit 25 is then set for the product of the determinedprime factors, in this instance 140. lf a stationary image has beenobtained on the face of tube CRT, it is determined that 149 is a factor.Then, 14() is successively multiplied by each of the prime factors 2, 4,5 and 7, count selection circuit 25 being set for each product todetermine the presence or absence of a stationary image on the face oftube CRT. It is found that only the product of factors 7 and 140 producea stationary image. As a result count selection circuit 25 is set at980. When a stationary image on the face of tube CRT is now obtained, itmay be presumed that 980 represents the correct number of clock pulsesactually recorded on timing track itl, since the total number desiredwas 1000, very nearly the same figure. However, as a further check tosee if 980 is the exact amount recorded, count selection circuit 25 issuccessively set at 979 and 981 to observe if the pulse image observedon the face of tube CRT shifts gradually to the left and then to theright. lf this occurs it is positively known that 980 represents theactual number of clock pulses recorded on timing track lill.

As has been previously explained, and as is well known to those skilledin the art, many of the components utilized in the system of Fig. l areconventional electronic components well known in the art. Specifically,variable frequency oscillators, amplifiers and squaring circuits,pulse-forming circuits, reading amplifier and squaring circuits,oscilloscopes having Y, T, and Z terminals, bistable ip-ops, andmagnetic reading and writing heads are well known in the art. Furtherdetailed consideration of the structure of these circuits, therefore, isobviously unnecessary. However, the structure of complementarypulseforming circuit 22, gate circuit 23a, clock writing circuit 12, andcounter 24 and count selection circuit 25 remains to be considered inmore detail.

Reference is now made to Fig. 4 illustrating in detail the complementarypulse forming circuit 22 of Fig. l. Complementary pulse forming circuit22, enclosed by dotted lines, is responsive to input signals SW forproduc- 13 ing complementary pulses CP1 and CP2 on output terminals P1and P2, respectively.

Essentially, complementary pulse forming circuit 22 is a modiedconventional blocking oscillator for producing very narrow sharp pulsesin response to wide input pulses.

Signals SW are applied to the grid of a first triode 400 through acoupling capacitor 401. The anode and cathode of triode 400 areconnected, respectively, to the anode and cathode of a second triode403. The cathodes of both triodes 400 and 403 are directly connected toground. A -15 volt reference potential is supplied to the grid of triode400 through a grid leak resistor 402 thereby maintaining triode 400below cut-off in the absence of a signal at the grid. The anodes of bothtriodes 400, 403 are connected to the lower terminal of a first windingW1 of a transformer T1. The upper terminal of winding W1 is connected-to a +180 volt supply through a currentlimiting resistor 404. Inaddition, a filter capacitor 419 is provided between Ithe upper terminalof winding W1 and ground.

A regenerative feedback circuit is provided by a second winding W2 oftransformer T1, the lower terminal of which is connected to the controlgrid of triode 403 through a current-lirniting resistor 406. The grid oftriode 403 is also connected to a -15 volt source through apotentiometer 405, the adjustable tap o-f which is directly connected tooutput terminal P1. The upper extremity of winding W2 is connected to a-15 volt source through a resistor 408 and to ground through a filtercapacitor 418, resistor -408 and capacitor 418 together forming an A.C.bypass filter for winding W2.

In parallel with winding W2 there is provided an antiringing circut orunidirectional current bypass circuit consisting of a resistor 415 and adiode 416 in series. In accordance with the conventions used throughoutthe present description, diode 416 is symbolized by an arrowhead and aline segment perpendicular to the arrowhead, the arrowhead symbolizingthe anode of the diode and the line segment signifying the cathode.

In accordance with the operation of conventional blocking oscillators, apositive signal appearing at the grid of triode 400, which is ofsufficient magnitude to overcome 'the negative bias of the triode,causes the triode to conduct. Momentary conduction of triode 400 causesa corresponding current signal in transformer winding W1. The currentsignal in winding W1 induces a voltage signal across winding W2 due tothe inductive coupling of the windings. The voltage signal appearingacross winding W2 is in phase with the positive signal impressed on thegrid of triode 400 thereby producing a positive or regenerativefeed-back voltage on the control grid of triode 403, thereby causing thecurrent in winding W1 to be further increased. As a result there is arapid rise of the anode current of triode 403 until the anode current ofthe triode reaches saturation.

Positive half-cycles of signals SW, appearing at the grid of triode 400,therefore, cause corresponding positive narrow pulses to be developed atthe grid of triode 403, wherein each positive pulse corresponds to theleading edge of a corresponding cycle of signals SW. These positivepulses, which are referenced to -15 Volts, are applied to terminal P1 assignals CP1 through potentiometer 405. Since triode 400 is maintainedbelow cut-off in the absence of a signal on the grid of the triode, itis obvious that the negative half-cycles of signals SW are ineffective.

Voltage signals corresponding to the voltage signals developed acrosswinding W2 are also developed across a third winding W3 of thetransformer. Winding W2 is provided for supplying output signals inphase with the signals developed across winding W2 but isolatedtherefrom in order to avoid excessive loading of winding W2 and topermit the use of a different reference voltage for each signal source.The lower terminal of winding W2 is directly grounded whereas the upperextremity of the winding is supplied from a -35 volt potential source 14through a clamping diode 412 and a current limiting resistor 411. Thusthe negative pulses generated at the upper extremity of winding W3 arereferenced to ground potential and clamped or clipped off at a maximumnegative value of -35 volts.

In Fig. 4 corresponding irl-phase terminal ends of the windings of atransformer are indicated by a dot at the corresponding ends of thewindings. The lower end of winding W1 is an in-phase terminal point withthe upper ends of winding W2 and W3 of the transformer. Summarizing,therefore, negative voltage pulses corresponding to the leading edge ofthe cycles of rectangular voltage signals SW are developed at the lowerextremity of winding W1. Corresponding positive voltage pulses aredeveloped at the lower extremity of winding W2 and correspondingnegative pulses are developed at the upper extremity of winding W3.

The negative pulses appearing at the upper extremity of winding W3 whichare referenced at ground potential and clipped at 35 volts, are appliedto the primary winding W4 of a stepdown transformer T2, the lowerterminal of winding W4 being grounded. The corresponding negative pulsesappearing at the upper extremity of the secondary winding W5 oftransformer T2, are fed to output terminal P2 and thus constitute thenegative output pulses CD2. In order to avoid ringing, a shunting pathfor possible positive pulses appearing across winding W5 is provided bya resistor 420 and a diode 421 connected in series across winding W5 asindicated, the junction of diode 419 and winding W5 being grounded.

Fig. 5 illustrates in detail the electronic gate circuit 23a, enclosedby dotted lines, suitable for operation in the system of Fig. 1. Originpulses Op are coupled, by a. coupling capacitor 500 to the anode lead504 of a coupling diode 501. Anode lead 504 is also connected to a 115Volt supply through a pull-down resistor 502. A clamping diode 503connects lead 504 to a -15 volt supply. As a result, the potential onlead 504 is pulled down toward a volt level but is not permitted to riseabove -15 volt level, i.e., is clamped at l5 volts, by the action ofclamping diode 503. Signals Op, appearing on lead 504, are thereforereferenced at a -15 volt level.

Cathode lead 505 of coupling diode 501 is directly connected to thesuppressor grid of a pentode tube 506. Lead 505, similar to lead 504, iscoupled through a pulldown resistor 512 to a -115 volt supply. Thepotential level of lead 505 in the absence of an Op signal, however,

is maintained at a -15 volt level by the clamping action of clampingdiode 503 operating through coupling diode 501. More specifically, whenthe potential level of lead 505 attempts to fall below -15 volts byvirtue of the l15 volt supply through pull down resistor 512;, diodes501 and 503 in series immediately cause conduction of current through acircuit path from the -115 volt supply through resistor 512, diodes 501and 503 and to the -15 Volt supply until the voltage drop acrossresistor 512 is sufficient to raise the voltage level of lead 505 to -15volts.

The true-complement output signal @Op from llip-tiop Q02 of Fig. l isapplied, through a pull-down diode 507, to lead 505. From the previousdiscussion with reference to Figs. 1 and 2, it will be remembered thatsignals Q01, are normally 1level or ground potential signals exceptduring a single clock pulse period of each revolution of drum 1corresponding to an origin pulse Op, at which time signal @op assumes aO-level or -15 volt value as indicated in Fig. 5. Normally, therefore,lead 505 being clamped at -15 volts or above, and signal Q01, having aground potential level, diode 507 is back biased. As a result an Opsignal, appearing on lead 505 is clipped at ground potential, becauseany rise above ground potential will cause diode 507 to conduct.

Signals Op, appearing on `lead 505, therefore have a lower limit of .-15volts and an upper limit of 0 volts or ground potential. On the otherhand, when signal @Op has a O-level value or -15 volt value and lead 505is at ground potential due to the presence of an Op signal, diode 507 isforward-biased thereby drawing current and rapidly pulling the potentialon lead 505 down to a l volt value. A charging capacitor 510 and a gridleak resistor 511 are also connected between lead 505 and ground, thepurposes of which are explained later on.

Signals Cpl are directly applied to the control grid of pentode fromterminal Pl of the complementary pulse forming circuit 22 of Fig. 4. Thecathode of pentode 506 is connected through a cathode resistor 513 toground, and the anode oi the tube is connected through a plate loadresistor 514 to a C- volt supply. The screen grid of the pentode ismaintained at +100 volts by a direct connection to the supply potential.

The values for cathode resistor 13 and plate resistor 514 are chosen tocause pentode 506 to be non-conductive so long as the suppressor grid ofthe tube is maintained at its l5 volt level irrespective of the presenceof a positive Cpl signal on the control grid of the tube. ln otherwords, in the absence of an origin pulse Op on the lead 505, signals Cplare ineffective to cause conduction of pentode 506. When the potentiallevel of the suppressor grid is raised from its l5 volt reference levelto ground potential due to the presence of an origin pulse Op on lead505, however, positive pulses Cpl are eflective to cause conduction ofthe pentode. As a result, negative pulse signals corresponding to theapplied Cpl pulses are developed at the anode of pentode 506. Thuspentode 506 operates as a coincidence gate tube inverting and amplifyingsignals Cpl applied thereto only when coincident with applied Opsignals.

ln order to insure coincidence between an origin pulse Op and a positiveCpl pulse, each Op pulse appearing on lead 505 is stretched orlengthened beyond its natural duration by an RC time constant circuitcomprised of capacitor 510 and resistors 511, 512. A l5 volt potentialcharge appears across charging capacitor 510 in the absence of an Opsignal. This charge is rapidly discharged through diode 501 when an Opsignal is present on lead 505 due to the forward bias of the diode 501.As the potential level on lead 505 tends to return to the l5 voltreference level, however, capacitor 510 must be recharged to a l5 voltpotential by current passing through resistor 512 from the -ll5 voltsupply. This current is divided between capacitor 510 and resistor 511.As a result the duration of each Op pulse appearing on lead 505 as shownin Fig. 5 is increased proportionally to the time constant of thetime-constant circuit comprised of capacitor 510 and resistors 511 and512.

1n order, however, to prevent the duration of an Op pulse on lead 505 toextend over two consecutive Cpl pulses, the potential level on lead 505is rapidly pulled down to the l5 volt reference level by signal @Opthrough pull-down diode 507 once a coincidence between an origin pulseand a single Cpl pulse has occurred. Referring brielly to Figs. l and 2,it is noted that once a Tp pulse is generated, representing coincidencebetween an origin pulse Op and a single Cpl signal, flip-flop Qpp isimmediately triggered to the l-representing state. As a result thetrue-complement output signal Qpp of the flip-flop changes from al-level to a 0level signal; i.e., from ground potential to -15 volts.The potential level of lead 505 is accordingly rapidly reduced to its l5volt reference level.

The negative signals appearing at the anode of pentode 506, whichcorresponds to positive input Cpl signals occurring coincident in timeto origin pulses Op, are applied to the control grid of a second pentode518 through a coupling capacitor 515. The control grid of pentode 518 isnormally maintained at ground potential by a diode 516 connected betweenthe grid and ground and a pull-up circuit comprised of a resistor 517connected 1h between the grid and a volt supply. The pull-up circuit ofthe grid has the added purpose of rapidly pulling the control grid backup to ground potential im mediately after each negative pulse appliedthereto. Pentode 513 is connected in the circuit as a conventionaltriode cathode follower having its anode and its screen and suppressorgrids connected directly to a -l-lOO volt supply, and its cathodeconnected to a volt source through a cathode load resistor 519. The lowimpedance negative output pulses Tp of the cathode follower circuit areclamped between maximum values of ground and l5 volts by a groundclamping diode 521 and a l5 volt clamping diode 520.

Fig. 6 illustrates in detail the clock writing circuit 12 of Fig. l.Clock writing circuit 12, enclosed by dotted lines in Fig. 6, isresponsive to output signals QW and QW of flip-flop QW of Fig. l forproducing current signals in recording head 11 having thecharacteristics for recording substantially rectangular clock pulses ontiming track 10 of drum 1. Signals QW are applied to a first input lead606 of a logical and circuit 601 and signals QW are applied to a firstinput lead 607 of a second logical and circuit 602, each logical andcircuit being indicated in the ligure symbolically by a semicircle witha dot Logical and circuits 601 and 602 are conventional and circuitswell 1irnown in the art having two or more inputs and a single outputand operative to produce a l-level output signal on its output when andonly when all inputs are simultaneously supplied with l-level inputsignals. Conversely, a logical and circuit of this class produces aO-level output signal whenever any one or more of the inputs aresupplied with a 0level signal. Typical logical and circuits of thisclass are described and illustrated in detail on pages 37-45 of HighSpeed-Computing Devices by Engineering Research Associates, published in1950 by McGraw-Hill Book Company, New York and London; and on pagesS11-514 of an article entitled Diode Coincidence and Mixing Circuits inDigital Computers" by Tung Chang Chen in the Proceedings of the IRE,volume 38, May 1950.

Each of the logical and circuits 601 and 602 is provided with a secondinput lead 621 and 622, respectively, which is directly connected to acommon lead 610 of switch S5. Lead 610 is coupled to ground by aresistor 604 and a capacitor 611 in parallel. In addition, lead 610- isconnected to a -115 volt source by resistor 605. lt is apparent,therefore, that when switch S5 is in the A position, lead 610 is atground potential by a direct connection thereto. Remembering that groundpotential represents a l-level potential in the present system, whereas-l5 volts corresponds to a O-level potential, inputs 621, 622 of logicaland circuits 601, 602 are provided with a l-level potential or signal solong as switch S5 is in the A position. When switch S5 is in the Aposition, therefore, signals QW and QW, impressed on inputs 606 and 607appear at the outputs 612 and 613, respectively, of the logical andcircuits 601 and 602.

The output signals of logical and circuits 601, 602 appearing on outputleads 612, 613 are directly applied to the individual control grids oftriodes 614, 615. The cathodes of both triodes 614 and 615 are connectedto ground and the anodes of the triodes are respectively connected tothe terminals of a single center-tapped winding 616 of head 11. Thecenter tap of winding 616 is returned to a +250 volt supply as shown. VAbleeder resistor 18 is connected between the anodes of triodes 614, 615in order to stabilize the recording circuit.

In operation recording circuit 12 functions in the following manner.When switch S5 is in the A position, signals QW and QW are appliedthrough logical and circuits 601 and 602 to the grids of triodes 614 and615. This occurs because lead 610 is maintained at ground potential,i.e., at the l-level value. At this time a steady current is drawn fromthe -115 volt source through resistor 605 and through lswitch S5 toground.

By momentary reference to Fig. 2 and from the previous discussion, it isapparent that signals QW and QW are complementary, ie., when signals QWare l-level signals, signals QW are O-level signals and converselysignals QW are l-level signals when signals` QW are -level signals. Thecircuitry associated with triodesl 614 and 615 is such that each triodeis cut-olf when the signal at its grid is a O-level or -l volt signal.When the signal at the grid of a triode is a l-level or ground potentialsignal, however, the triode causes current to ow through itscorresponding half of winding 616 in the direction indicated by thearrows. Thus when signal QW is a l-level signal, current ows through theleft-hand half of winding 616 in the direction indicated, and whensignal QW is a l-level signal current flows through the right-hand halfof the winding yas indicated by a corresponding arrow. Consequently,current alternately ows through Winding 11 in two opposite directions,one direction corresponding to 1- level values of signals QW, and in theopposite direction corresponding to O-level values of signals QW orwhich amounts to the same thing, l-level value for signals QW.

With switch S5 in the B position, the current previously drawn throughresistor 605 from the -115 volt source to ground now returns to groundthrough resistor 604. Resistors 604 and 605 form a series voltagedivider between ground and the -115 volt source, values for theseresistors being chosen to maintain lead 610 at a suitable negative valueto cause logical and circuits 601, 602 to cut off or isolate signals QW,QW from the grids of triodes 614, 61S. In order to enable the potentialon lead 610 to drop from ground to the predetermined negative potential,however, capacitor 611 must be charged by a portion of the currentflowing through resistor 605. Thus resistor 605 in series with resistor604 and capacitor 611 in parallel form an RC time constant circuitcausing the potential on lead 610 to drop when switch S5 is put into theB position. This causes the signals appearing on leads 612 and 613 to begradually reduced in amplitude. In this manner, the recording current ofhead 11 is gradually reduced to avoid generation of unwanted transientcurrent signals in the head when clock-pulse recording is interrupted bythrowing switch S6 from the A to the B position.

Reference is now made to Fig. 7 wherein there is illustrated in detailthe counter 24 and the count selection circuit 25, both enclosed bydotted lines, suitable for operation in the system of Fig. 1. Aspreviously mentioned, counter 24 of Fig. 1 may be any conventionalcounter capable of counting negative pulses Cp2 impressed thereon andproducing complementary pairs of binary or "m0-level Output Signals Q1,Q1; Q2, Q2; Q3, 3; Qn 6) indicating, in a true binary or a binary-codednumbering system, the count of the counter. In addition, it waspreviously mentioned that counter 24 must be capable of counting signalsCpz only when signals Q,p -and @Op are respectively O-level and l-levelsignals, and that counter 24 be reset to zero whenever signals Qop and@op are respectively l-level and 0-level signals. The specificembodiment of counter 24 illustrated in Fig. 7 is responsive to signalCpz, Qop and @Op impressed thereon for producing signals Q1, Q1 Qn, Qnindicating at any instant the count contained in counter 24 at thatinstant in a true binary numbering system.

As shown in Fig. 7, counter 24 comprises a series of conventionalbistable flip-Hops Q1', Q2', Q3 Qn. After each pulse CP2 has beenapplied to counter 24, each of the llip-ops Q1' to Qn stores a singlebinary digit in a corresponding binary place of the binary numberrepresenting the count of the counter. In the counter 4illustrated,ilip-ilop Q1' stores the binary digit corresponding to the leastsignificant lbinary place, Q2 stores the next to the least significantbinary digit, and so forth, Qn storing the most significant binary digitof the binary number representing the count of the counter. As` is wellknown in the art, a conventional binary numbering system may be definedas a numbering system wherein a quantity is represented by a group ofbinary digits having weights or powers of two. Accordingly, each binarydigit of a group has a weight double that of the immediately lesserorder or significant binary digit and onehalf that of the immediatelygreater order binary digit of the group. Accordingly, a binary onestored in flip-flop Q1 has a weight or signicance of l, a binary lYstored in flip-op Q2 has a weight or significance of 2, a binary lstored in flip-op Q3 has a weight or signiiicance of 4, and so forth inascending powers of 2 with a binary l stored in flip-iiop Qn having alweight or sign-iiicance of 2"1. In accordance with the conventionsherein emfployed, therefore, l-level true output signals Q1, Q2, Q3 Qn,produced by ip-ops Q1', Q2', Q3 Qn' represent respective weights of 20,21, 22 2-1. Conversely, a O-level true output signal such as Qk of aflipop, indicating that the flip-.ilop is storing a binary O,corresponds to a 0 weight or value.

A true binary flip-Hop counter for counting pulses CP2 wherein ip-opsQ1' to Qn simultaneously assume their succeeding count states uponreception of each CP2 count signal is fully described and claimed inco-pending U.S. patent application, Serial No. 245,860, for High- SpeedFlip-Flop Counter, by Eldred C. Nelson, tiled September l0, 1951. Thediscussion herein of counter 24 is accordingly brief, emphasis beingplaced on the manner in which the Nelson counter is modied to be re-setby signals Qop and @op in the manner previously discussed.

In order to facilitate an explanation of the mechanization of counter 24in relation to the state of ilip-ilops Q1 to Qn for each count, logicalBoolean algebra is utilized to identify the signals applied to the l andthe 0 inputs of the ilip-flops. Logical Boolean algebra, as is wellknown in the art, is based on binary representation of signal values,and is utilized to indicate the mathematical or physical relationshipbetween various binary signals. There are two basic operations inBoolean algebra, commonly referred to as the logical and operation andthe logical or operation. Signals representing binary values which arecombined in a logical Boolean function by a logical and symbol, areanalogous to the application of the signals to separate inputs of alogical and circuit. Signal symbols connected in a Boolean equation bylogical or symbols are analogous to the application of the signals tothe separate inputs of a logical or circuit. A logical and circuit, asdened herein, is a circuit for receiving a plurality of binary inputsignals and for producing a single output signal having a l-level valuewhen, and only when, all the input binary signals are simultaneously1-leve1 signals. A logical or circuit may be dened as a circuitresponsive to a plurality of binary input signals for producing a singleoutput signal having a l-level value when at least one of the inputsignals applied thereto is a l-level signal. A comprehensive discussionof the application of logical Boolean algebra to the mechanization oflogical gating circuitry is found in an article entitled An AlgebraicTheory for Use in Digital Computer Design by Eldred C. Nelson in the IRETransactions-Electronic Computers, September 1954, pages l2 to 2linclusive.

Table I below illustrates the stable states of ilip-ilops Q1 to Qncorresponding to successive decimal counts of counter 24. In the table,the decimal equivalent counts of the counter appear in the left-handcolumn of the table and the corresponding stable states of the ilipflops`are indicated symbolically by l and 0 digits in the remaining columnsof the table. It is assumed for convenience `thatilip-llops which may beprovided in counter 24 ybetween flip-ilops Q3 and Qn are all in theirO-repreil@ senting states for the decimal equivalent values included inthe table.

Although various symbols have been utilized for representing the logicaland and the logical or functions of a Boolean equation, a dot orparenthesis Will be exclusively utilized herein to represent the logicaland function and a plus sign between signal symbols will herein beutilized to indicate the logical or function. The signals applied to thel-input and the O-input of a flip-flop of counter 24 will hereinafter beindicated by a 1 and a 0, respectively, followed by the symbolidentifying the flip-flop. For example, the signal applied to thel-input of fiip-iiop Q1 will be identified by the symbol lQl. Similarly,the signal applied to the O-input of flip-op Q1 will be identified bythe symbol OQl.

From Table I above it is noted that flip-iiop Q1 is triggered to itsopposite state upon each succeeding count. Thus, flip-flop Q1alternately stores a binary l and a binary upon each succeeding countpulse applied to counter 24. Since, as previously explained, flip-fiopsQ1 to Qn of counter 24 are each triggered to its opposite state whenevera signal is simultaneously applied to both its 1 and its O inputs, anexpression representing the triggering function of flip-flop Q1', may,therefore, be expressed logically as:

A further study of Table I indicates that each of the flip-flops Q2 toQn' is triggered to its opposite state on the succeeding pulse only whenall iiip-iiops representing lower order binary digital places of thecounter are presently in their respective 1-representing states. At allother times each of the iiip-ops Q2' to Qn are unaffected by a change incount of counter 24. For example, fipflop Q2 alters its state on thesucceeding pulse whenever Q1 is now in the l-representing state, butremains unchanged in state when iiip-flop Q1' is presently in the 0-representing state. Similarly, fiip-flop Q3 is changed to the oppositestate as indicated in Table I when ip-flops Q1 and Q2' are bothpresently in their l-representing states. Thus, the logical Booleanequation representing the 1- `and O-input signals to each of theflip-ops Q2 to QTL may be written as:

Although the above logical Boolean expressions describing the inputsignals to flip-fiops Q1 to Qn of counter 24 satisfy the conditionsillustrated in Table I above, the logical expressions must now bemodified to include the reset functions provided by signals Qop and @oppreviously discussed. It has been determined, from the discussion ofFig. 1, that counter 24 must count pulses CP2 so long as signals Qop and@op are respectively O-representing and 1-representing signals. It wasfurther established that when signals QOp and QCD have respective1-level and 0- level values, counter 24 is reset to its 0 value, i.e.,iiipflops Q1 to Qn are all reset to their respective O-representingstates. More specifically, the above functions describing the inputsignals to the flip-iiops included in counter 24 must incorporatesignals Qop and @Op in a manner whereby none of the fiip-flops may betriggered to its l-state unless Qop and Qop are respectively 0level andl-level signals. Since signals Qop and @op are complementary, this maybe accomplished by incorporating by a logical and function signal QDI,in the function describing the signals to the l-inputs of each of thefiip-ops in the counter. Thus, the logical functions for the inputsignals to the flip-flops Q1 t0 Qn', including this additional term, maybe expressed as follows:

Conversely, it is desired that all of the flip-ops Q1 to Qn besimultaneously triggered to their O-representing states whenever signalsQop and QCD are respectively l-level and 0level signals. This may bereadily accomplished by adding the term Qop, as a logical or function ineach of the above functions describing the O-input signals of theflip-flops Q2 to Qn', signals CP2 being always applied to the 0 input offiip-op Q1. The resulting logical Boolean equation defining the inputsignals applied to the 1 and the 4O inputs of each of the flip-flops incounter 24, therefore, become:

The mechanization of counter 24 from the logical Boolean equation abovederived readily follows when it is remembered that each logical andfunction included in an equation is provided in the counter by acorresponding logical and7 circuit. Similarly, each logical or functionof an equation is provided by a corresponding logical or circuit in thecounter. Each logical and circuit in the counter is symbolicallyindicated in Fig. 7 as in Fig. 6. Each logical or circuit of the counter24 is represented symbolically by a semicircle with a plus `sign in thesymbol. Foiexample the and function @WCM defining the 1 input signals1Q1 of Hip-flop Q1 is mechanized in the counter 24 by a logical andcircuit 701 for receiving signals Qop, CD2 and for providing `outputsignals which are impressed on the 1 input of flipflop Q1. A logical andcircuit 702, for receiving input signal Qop, Q1, Cpg, and for producingoutput signals which are impressed on the 1 input of flip-flop QZ, isprovided for satisfying the logical and function Qap-QlCpZ defining thesignals to be applied to the 1 input of ipflop Q2". The logical equationdefining signals 0Q2 impressed on the input of flip-flop Q2' may beanalyzed as an or function QOH-Q1 and an and function combining signalsQop-i-Q1 with signals CD2. In mechanizing the above function, therefore,a logical "or circuit 703 is provided for receiving signals Qop, Q1 andfor providing output signals which are applied to a first input of lalogical and circuit 704. Signals CP2 are applied to a second input `oflogical and circuit 704, the output signals of logical and circuit 704being directly applied to the O input of flip-flop Q2. In a similarmanner, the remaining logical equations defining the input signals toflip-flops Q3' to Qn of counter 24 are satisfied by logical and andlogical or circuits provided in the counter 2'4 of Fig. V7. Since themechanization of the remaining functions directly follows from anexamination of the corresponding logical equations, further explanationof the mechanization of the counter 24 is, therefore, deemedunnecessary.

Count `selection circuit 25 is provided for receiving signals Q1, Q1 toQ2, Qn produced by counter 24 and for producing first and second l-levelpulse output signals C1 and C2 when a first and a second count,respectively, are registered in counter 24. As previously explained inconnection with Fig. 1, the first and the second counts of counter 24,when signals C1 and C2 are respectively produced, are selectivelydeterminable by count selection circuit 25. This is accomplished byproviding two sets of single-pole double-throw selector switches S1 toS1, and S1' to Sn', each having stationary contacts A and B and a singlemovable contact. The A and the B contacts of each switch arerespectively connected to the true and the true-complement outputs of acorresponding one of the fiip-fiop Q1' to Q2'. Thus, the A contacts ofswitches S1 and S1' are both connected to the true output Q1 offlip-flop Q1', and the B contacts of both switches are directlyconnected to the true-complement output Q1 of the flip-fiop and so on.

The movable contacts of switches S1 to S,L are directly connected tocorresponding yseparate inputs of a logical and circuit 711, and themovable contacts of switches S1 to Sn' are respectively connected tocorresponding separate inputs of a logical and circuit 712. Outputsignals C1 are directly derived from the output of logical and circuit711, and output signals C2 are directly derived from the output of thelogical and circuit 712. For convenience, the signals appearing on themovable contacts of switches S1, S2, S3, S,L are respectively designatedA1, A2, A3, A2. In a similar manner the signals appearing on the movablecontacts of switches S1', S2', S3', Sn' are respectively designated assignals A1', A2', A3', An. In accordance with Boolean algebra,therefore, signal C1 and C2 may be defined by the logical function:

A l-level C1 signal, therefore, will be produced whenever signals A1 toA,L are all simultaneously l-level signals, and will have a O-levelvalue whenever any one of these signals has a O-level value. Similarly,`signals C2, produced by logical and circuit 712, will have a 1- levelValue when, and only when, signals A1 to An are all simultaneouslyl-level signals. Accordingly, the values of signals Q1, Q1 to Q2,required for producing a 1-level C1 signal will be dependent upon thesetting of the switches S1 to S2 and, similarly, the values of signalsQ1, Q1 to Q2, Q2 required for producing a l-level C2 signal will dependupon the setting of the switches S1 t0 Sn.

By way of illustration, assume that it is desired to produce a l-levelC1 signal at a particular count of counter 24, represented by flip-HopsQ1', Q2', Q3' and Qn' storing,

respectively, binary 1, 1, 0, and `0. True output signals Q1, Q2, Q3,and Q,L will, therefore, have respective values of 1, l, 0, and 0, andthe true-complement output signals Q1, Q2, Q3 and Q2 will haverespective values of 0, 0, 1 and l. In order to obtain 1level signalsA1, A2, A3 and A,L from switches S1, S2, S3 and S7L at this count,switches S1 and S2 must be in their A position, and switches S3 and Snmust be in their B position as illustrated. If it is desired to producea C2 1-level pulse on a count of counter 24 represented by binary digits0, l, 1, and 0 stored respectively in fiipiiops Q1', Q2', Q3' and Qn,Switches S1' and Sn must be in their B positions and switches S2' and S3in their A positions.

In conclusion, therefore, there has been disclosed a system foraccurately and reliably recording a desired number of clock pulses within-phase overlap on the timing track of a rotating memory drum. It hasbeen demonstrated that the system of the present invention is adapted torecord a dired number of clock pulses on the timing track of the drumirrespective of variations of the angular velocity of the drum, thetiming track thus recorded being free from transients or timemodulation. In addition it has been shown that the recording system ofthe present invention is adapted to accurately determine the number ofclock pulses and the phase overlap of a previously recorded timingtrack. It has further been demonstrated that the recording system of thepresent invention is completely free from mechanical errors.

What is claimed is:

1. A system for recording a desired number of timing pulses within-phase overlap on a timing channel of a rotating recording drum, saidsystem comprising: first variable frequency means coupled to therecording drum for continuously generating timing pulses and forrecording said timing pulses on the channel of the drum, second meanscoupled to the recording drum and responsive to the rotation thereof forproducing revolution-indicating signals indicating the completion ofeach revolution of the drum; third means coupled to said first means andsaid second means and responsive to said timing pulses 'and saidrevolution-indicating signals for counting said timing pulses andproviding output signals indicating the instant during each revolutionof the drum when the desired number of timing pulses has been recorded;and fourth means coupled 'to said second means and said third means andresponsive to said revolution-indicating signals and said output signalsfor comparing the time of occurrence of said revolution-indicatingsignals with the time of occurrence of said output signals during eachof said revolutions to indicate the necessary variance of frequency ofsaid first means for recording the desired number of clock pulses within-phase overlap on the drum.

2. A system for recording a desired number of clock pulses with in-phaseoverlap on the timing track of a rotating recording drum, said systemcomprising: recording means including variable frequency means coupledto the rotating drum for continuously generating clock pulses and forrecording said clock pulses on the timing track thereof;revolution-indicating means coupled to the rotating drum and responsiveto the rotation thereof for producing an indicating signal once duringeach revolution of the drum to indicate the completion of therevolution; counting means coupled to said recording means and saidrevolution-indicating means and responsive to said clock pulses and saidindicating signals for producing count selection signals, one of saidcount selection signals being produced during each revolution of thedrum at the instant the desired number of clock pulses has been recordedon the timing track during the revolution; and'coincidence means coupledto said revolution-indicating means nad said counting means to 'receivesaid indicating signals and said count selection 23 signals forindicating coincidence between said indicating signals and said countselection signals during each of said revolutions, thereby indicatingwhen the desired number of clock pulses has been recorded with in-phaseoverlap on the timing track of the recording drum.

3. A clock pulse recorder for recording a desired number of clock pulseson a timing track of a continuously rotating magnetic drurn, saidrecorder comprising: a variable frequency generator coupled to themagnetic drum for generating clock pulses, means responsive to saidclock pulses for recording same on the drum, an analog-to-digitalconverter coupled to the drum and responsive to the rotation thereof forproducing an origin pulse during each revolution of the drum indicatingthe time of completion of the revolution; and a counting circuit coupledto said generator and said analog-to-digital converter responsive tosaid clock pulses and said origin pulses for producing count selectionsignals indicating the instant during each revolution of the drum whenthe desired number of clock pulses has been recorded on the timingtrack, thereby indicating the necessary variance of said generator forrecording the desired number of clock pulses on the timing track within-phase overlap.

4. A system for accurately recording a selected number of clock pulseswith in-phase overlap on the timing track of a rotating magnetic drum,said system comprising: a clock pulse recorder coupled to the magneticdrum responsive to generated clock pulses for recording said clockpulses on the timing track; a revolution indicator coupled to themagnetic drum and responsive to the rotation thereof for producing anorigin pulse to indicate the beginning of each revolution of the drum; acounter circuit coupled to said clock pulse recorder and said revolutionindicator and responsive to said clock pulses and said origin pulses forcounting said clock pulse signals and for developing a count selectionpulse during each revolution of the drum indicating the instant when thedesired number of clock pulses has been recorded on the timing track ofthe drum during the revolution; and a comparison circuit coupled to saidrevolution indicator and said counter circuit and responsive to saidorigin pulses and said count selection pulse for comparing the timerelationship between an origin pulse and a count selection pulse duringeach revolution.

5. The system defined in claim 4 wherein said comparison circuitincludes an oscilloscope for indicating the desired time coincidencebetween said origin pulses and corresponding pulses of said countselection pulses.

6. The system defined in claim 4 wherein said recorder includes anadjustable oscillator for generating a sine Wave and further includes asquaring circuit coupled to said oscillator and responsive to said sinewave for producing a corresponding output square Wave, a firstpulseforming circuit coupled to said squaring circuit and responsive tosaid square wave for developing a first series of triggering pulses,each of said irst series of triggering pulses being produced in responseto the trailing edge of a cycle of said square wave, a secondpulse-forming circuit coupled to said squaring circuit and responsive tosaid square wave for developing a second series of triggering pulses,each of said second series of triggering pulses being developed inresponse to the leading edge of a cycle of said square wave, a bistableflip-flop coupled to said tirst and second pulse-forming circuits andhaving 1 and 0 inputs responsive respectively to said rst and secondseries of triggering pulses and producing complementary two-levelvoltage output signals indicating the stable state of said bistableflip-flop at any instant, and a clock-writing circuit coupled to saidbistable flip-op and responsive to said voltage output signals forrecording said clock pulses on the timing track of the drum.

7. The system defined in claim 4 wherein said recorder includes meansfor simultaneously producing a positive triggering pulse and a negativetriggering pulse in response to each clock pulse produced by said clockpulse recorder; and wherein said revolution indicator includes a readingcircuit coupled to the drum and responsive to a single origin indiciumrecorded thereon for producing an electrical origin signal once duringeach revolution of the drum, a gate circuit coupled to said clock pulserecorder and said reading circuit and responsive to said positivetriggering pulses and said origin signals for producing a gatedtriggering pulse once during each revolution of the drum correspondingto one of said positive triggering pulses received by said gate circuitin time coincidence With one of said origin signals, and a bistableflip-op coupled to said clock pulse recorder and said gate circuit andhaving 1 and 0 inputs responsive respectively to said gated triggeringpulses and said negative triggering pulses for producing said originpulse.

8. The system delined in claim 4 wherein said counter circuit includes acounter for counting said clock pulses and for producing binary outputsignals indicating the count contained in said counter `at any instant,said counter being reset to zero by each of said origin pulses, and saidcounter circuit further including a count selection circuit coupled tosaid counter and responsive to said binary output signals for developingsaid count selection pulses, said count selection circuit havingswitches for receiving said binary output signals and for selectingdesired ones of said binary output signals to produce selected binaryoutput signals, and a logical and circuit coupled to said switches andresponsive to said selected binar/ output signals for producing saidcount selection pulses.

9. A system for recording a selected number of clock pulses on thetiming track of a rotating memory drum, said system comprising: aclock-pulse recording circuit coupled to the drum for continuouslyrecording clock signals thereon, said recording circuit including avariable frequency generator for producing a symmetrical wave, apulse-forming circuit coupled to said generator and responsive to saidsymmetrical Wave for producing a positive and a negative triggeringpulse in response to each cycle of said symmetrical Wave, a recordercircuit coupled to said generator, said pulse-forming circuit, and thedrum to receive said symmetrical Wave and said negative triggeringpulses for recording said symmetrical wave on the timing track; arevolution indicating circuit coupled to said pulse-forming circuit andthe drum and responsive to said positive and negative triggering pulses,and the rotation of said drum for producing a revolution indicatingsignal once during each revolution of the drum indicating the completionof the revolution, said revolution indicating circuit including areading circuit coupled to the drum and responsive to a single pulserecorded thereon for producing an origin pulse once during eachrevolution of the drum, a gate circuit coupled to said pulse-formingcircuit and said reading circuit to receive said positive triggeringpulses and said origin pulses for `selectively gating one of Saidpositive triggering pulses to produce a selected triggering pulse inresponse to time coincidence between a positive triggering pulse and anorigin pulse, a bistable ilip-op coupled to said pulse-forming circuitand said gate circuit and having 1 and O inputs responsive,respectively, to said negative triggering pulses and said selectedtriggering pulses for producing said revolution indicating signal; acounting circuit coupled to said pulse-forming circuit and saidrevolution indicating circuit and responsive to said negative triggeringpulses and said revolution indicating signals for producing a countselection signal once during each revolution of the drum indicating theinstant during the revolution that the selected number of clock pulseshave been recorded, said counting circuit including a counter responsiveto said negative triggering pulses and said revolution indicatingsignals for counting said negative triggering pulses and for resettingto a zero count upon reception of each of said revolution indieatingsignals, said counter producing count output signals indicating thecount in said counter at any instant, a count selection circuit coupledto said counter and responsive to said count output signals forproducing said count selection signals; and a time-comparison circuitcoupled to said revolution indicating circuit and said counting circuitand responsive to said revolution indicating signals and said countselection signals for indicating the necessary frequency adjustment ofsaid variable frequency generator to cause each of said revolutionindicating signals to occur in time coincidence with a count selectionsignal thereby indicating that said recording circuit has been properlyadjusted for recording the desired timing track.

References Cited in the le of this patent UNITED STATES PATENTS HoglundAug. 22, Ignalls Oct. 30, Cohen et al Oct. 14, Ward Aug. 3, Witt June14, Deppy May 15, Kuder Sept. 4, Lubkin et al. Sept. 25, Slutz May 29,Begun et al. Aug. 20, Lubkin July 30,

